Abstract
Flicker or 1/f noise in metal-oxide-semiconductor field-effect transistors (MOSFETs) has been identified as the main source of noise at low frequency. It often originates from an ensemble of a huge number of charges becoming trapped and de-trapped. However, as a deviation from the well-known model of 1/f noise is observed for nanoscale MOSFETs, a new model is required. Here, we report the observation of one-by-one trap activation controlled by the gate voltage in a nanowire MOSFET and propose a new low-frequency-noise theory for nanoscale FETs. We show that the Coulomb repulsion between electronically charged trap sites prevents the activation of several traps simultaneously. This effect induces a noise reduction of more than one order of magnitude. It decreases when the electron density in the channel is increased due to the electrical screening of traps. These findings are technologically useful for any FET with a short and narrow channel.
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Introduction
In electronics, noise refers to unwanted or parasitic random signals overlying the useful signals. For most electronics applications, such as amplifiers, memories or digital processing, metal-oxide-semiconductor field-effect transistors (MOSFETs) are the basic constituent of circuits. However, whereas scaling is required for high levels of integration and an increase of working speed, for instance, low-frequency noise is progressively becoming a serious issue for continuous device scaling1. Power spectrum current noise in MOSFETs at low frequency follows the 1/f law, meaning that the noise spectrum is inversely proportional to frequency f on a logarithm scale. The 1/f noisef is generally interpreted as the superposition of random events of charge trapping and de-trapping from defects randomly distributed in the gate oxide (for example, SiO2) near the semiconductor channel (for example, Si)2,3 (Fig. 1a). In shrunk MOSFETs, the number of electrically active defects is reduced, and the low-frequency noise begins to deviate from the 1/f characteristics3,4,5,6. Finally, in submicrometer MOSFETs (for example, <100×100 nm), only a few traps exist, and we observe discrete switching of the drain current between two (or more) levels under constant bias conditions2,3,4,5,6,7,8,9,10 (Fig. 1b). These fluctuations, known as random telegraph signals (RTSs), give a Lorentzian distribution in the power spectrum current noise. In other words, 1/f noise, resulting from an averaged ensemble of individual RTSs, is no longer valid in ultrasmall MOSFETs. Therefore, the electrical properties of individual RTS need to be understood to elucidate the noise behaviour in such nanoscale MOSFETs.
Here, we show that one-by-one activation of RTSs at room temperature can be controlled by the gate voltage of nanoscale MOSFETs. This one-by-one activation is attributed to Coulomb repulsion between electrons trapped in neighbouring defects5,11,12. We establish equations for low-frequency noise in such nanoscale MOSFETs and demonstrate a drastic reduction of this low-frequency noise. Moreover, we show that electrical screening by the electrons in the semiconductor channel reduces this one-by-one activation.
Results
Device structure
Scanning electron microscope top and schematic side views of the device are shown in Figure 1c. Large undoped silicon-on-insulator (SOI) channels with oxide thickness tox=400 nm are locally constricted by e-beam lithography and thermally oxidized to form a 40-nm-thick upper oxide (see Methods). The current characteristics are determined by the constricted channel whose width (W) and length (L) after the oxidation are 15 and 50 nm respectively13. The Si substrate is used as the back-gate. Such a small wire channel makes the MOSFET useful as a high-charge-sensitivity electrometer with single-electron resolution14,15,16 and thus suitable for a clear observation of RTS at room temperature. Electrons are trapped by oxide defects surrounding the SOI channel at a tunnelling distance (for example, <3 nm)2. For a basic equivalent circuit (Fig. 1c), we consider the capacitance CG between the gate and trap site and tunnelling capacitance CJ between the channel and trap site.
RTS amplitude in an Si nanowire transistor
Trapping and de-trapping of a single electron by and from a single trap close to the Si channel induce a two-level fluctuation of the drain current called RTS noise due to the electrostatic effect caused by the electron. This RTS noise gives us access to precise information, such as the trap depth (that is, its distance in the oxide from the Si/SiO2 interface) and gate capacitance CG. In this section, we focus on the analysis of RTS noise amplitude in the nanoscale FETs and, in addition to the aforementioned parameters, we also introduce an effective trap charge, q*, originating from the trapped electron. Figure 2a explains the mechanism of RTS. Let I be the average value of the drain current, Id and ΔI the amplitude of RTS signal. When an electron is trapped by a defect, the electrostatic effect induced by q* shifts current Id as a function of back-gate voltage VBG by ΔVFB. As a result, at a constant gate voltage, this shift corresponds to a small decrease in Id. When an electron is de-trapped from the defect, Id returns to its initial value upon electron de-trapping, thus giving rise to the two-level RTS noise. When CGCJ17,18, simple electrostatics leads to ΔVFB=q*/CG, and from the slope gm=∂I/∂VBG of the I–VBG curve (gm is the transconductance of the transistor), we get ΔI=gmΔVFB. Thus, the basic RTS equation is
This equation is widely used for flat band voltage VFB fluctuation17 as well as for quantifying the behaviour of single-electron memories14,18. The effective charge q*, which is used instead of the electron unit charge q, depends on VBG and will be discussed later. Basically, we consider q*=q at low gate voltage, that is, in the subthreshold region19 (VBG<VFB=12 V here), and q*<q above VFB. Figure 2b shows two examples of RTSs measured in our Si nanowire MOSFET. The upper panel shows basic two-level current fluctuation behaviour, and the lower one shows a more sophisticated three-level current fluctuation, which will be discussed later (see section Coulomb repulsion analysis). Figure 2c shows I–VBG, ΔI–VBG and gm–VBG characteristics. We distinguish the RTS contributions of five traps in the ΔI–VBG curve from a detailed analysis of the time dynamics of the RTS signal (see next section). Then, from the data in Figure 2c (limited below VFB=12 V to assume q*=q) and from equation (1), we obtain CG=0.91±0.18 aF, which is a realistic value from the viewpoint of device geometry. This proves the validity of equation (1) related to RTS amplitude. Such a clear RTS amplitude dependence of the transconductance gm for several traps is obtained because the oxide thickness between the channel and gate is much larger than the trap depth (distance from the Si nanowire, see Fig. 1c), that is, CG is much smaller than CJ, and because the device dimensions (in particular the width) are much smaller than the Debye screening length (here ∼110 nm at room temperature and for an Si nanowire doped at 1015 cm−3); otherwise, the trapped charges in the defects would make the RTS analysis more complicated. As a consequence, such RTS measurement in a nanoscale MOSFET is a highly effective metrology tool for evaluating gate capacitances in the subattofarad range, which is very difficult with other techniques.
Trap occupancy probabilities
To identify the RTS signal from each trap site, we record the time duration of the high and low currents for a large number of such RTS fluctuations, as shown in Figure 2b. According to the standard statistical analysis2, we deduce the average electron capture time (τc) and emission time (τe). Figure 3a shows the VBG dependence of τc and τe. We can identify four sets of τe and τc at different values of VBG, corresponding to four traps and, more interestingly, can see that the four RTSs become active in turn with increasing VBG. Hereafter, we refer to those sites as traps 1–4 as shown in Figures 2c and 3a. For trap i (i=1–4), the probability that a trap is occupied by an electron gi=τe/(τe+τc) also shows a clear one-by-one activation of RTSs. The behaviour of such one-by-one activation of RTSs seems to be unnatural in the well-known RTS theory because it means that trap sites have well-aligned energy levels, although the energy levels are expected to be randomly distributed in space and energy. We will show below that Coulomb repulsion between electrons trapped by a defect can satisfactorily explain this behaviour.
Coulomb repulsion analysis
For the analysis of the Coulomb repulsion, let us return to the three-level RTS observed in the bias range 20.5 V<VBG <23.5 V (Fig. 2b). The three-level RTS implies two traps active simultaneously with the same ΔI. This is attributed to trap 4 and another trap (trap 5). Upper (U), middle (M) and lower (L) levels mean that no trap, only one trap and both traps are filled with electrons, respectively. In this bias range, the histograms of the U, M and L levels in Id follow a Gaussian distribution with a relative amplitude that depends on VBG. Figure 3c shows histograms at VBG=20.5, 22 and 23.5 V. Because the amplitudes of the peaks depend on VBG, normalization of each amplitude allows evaluation of probabilities PU, PM and PL of U, M and L levels, respectively, in three-level RTSs (Fig. 3d). With g4 and g5 as the occupancy probabilities of traps 4 and 5, we get PU=(1−g4)(1−g5), PM=g4(1−g5)+g5(1−g4) and PL=g4g5 for the trap conditions illustrated in the inset of Figure 3d. To evaluate PU, PM and PL, we first use the usual g partition function for traps 4 and 5 (g4 and g5):
where is the difference between the trap potential energy (i=1 to 5) and Fermi energy at VBG=0 V, is CJ of trap i, CG the back-gate capacitance (see Fig. 1d), k the Boltzman constant, T the temperature, q the electron charge and VBG the back-gate voltage. However, equation (2) leads to poor fits (Supplementary Figure S1). To obtain satisfactory fits for PU, PM and PL, we use
by introducing an additional term gj′ ϕij (equation 1). The gj′ ϕij corresponds to the Coulomb repulsion potential between trap i and trap j, weighted by occupancy probability gj′ of the interacting trap j. Using equation (3) instead of equation (2) for the probabilities PU, PM and PL allows us to obtain a reasonable fit as shown in Figure 3d. From this analysis, we can extract occupancy probabilities g4′ and g5′ of traps 4 and 5 as reported in Figure 3b.
The qualitative meaning of this modified equation (equation 3) can be simply illustrated with a band energy diagram (Fig. 4a) showing how traps 4 and 5 cause the three-level RTS. The key point is a competing effect, quantified by hi, of Coulomb repulsion gjϕij and VBG-induced potential drop CGVBG/CJi of the trap energy level, where hj can be given by
In the range of VBG between 18 and 23.5 V, the energy level of trap 4 aligns close to that of trap 5, which leads to three-level RTSs. However, as trap 5 is located deeper from the channel than trap 4, as shown in Table 1 (see Methods for the determination of trap depth), removing an electron from trap 5 is harder than removing one from trap 4. More importantly, the Coulomb repulsion is larger than the potential drop of trap sites caused by the applied bias VBGs; that is, h5 is positive. Therefore, in this VBG range (18–23.5 V), we can now describe the coupled behaviour of traps 4 and 5 (Fig. 3b). As occupancy probability of trap 4 increases with VBG, energy level of trap 5 increases (kink in g5′). Because the rise in the energy level is enough to get complete blockade, occupancy probability of trap 5 increases and pushes up energy level of trap 4 (decrease of g4′). When trap 5 is almost always filled, occupancy probability of trap 4 increases again (increase of g4′). The estimated Coulomb repulsion between traps 4 and 5, ϕ45, is 110 meV (see Table 1).
This Coulomb effect also explains the one-by-one activation of RTSs shown in Figure 3b, that is, the fact that there is no overlap of the occupancy functions of traps 1, 2 and 3. The data are well separated along the VBG axis and equation (3) well reproduces this behaviour. This means that the shaded areas in Figure 3b correspond to high Coulomb repulsion as indicated by the positive values of hj (Fig. 4b) for traps 1, 2 and 3. The more complicated curve for VBG>18 V corresponds to the interacting behaviour between traps 4 and 5 as discussed above. As a consequence, it could be concluded that the energy levels of traps when empty are close to each other, which is natural and more feasible given a similar chemical structure. These considerations based on equations (3) and (4) can explain the one-by-one activation of RTSs shown in Figure 3b, that is, no overlap (shaded areas in Fig. 3b) between each gi′s at positive hj in particular VBG regions of Figure 4b.
This idea can also be explained by an analysis of ϕij. From the data shown in Figure 2c, using equation (1) and assuming CG does not depend on VBG (CG=0.91±0.18 aF, see above), we can calculate the effective charge q* for each trap (Table 1). Because tox=400 nm and SiNW thickness is 15 nm, the oxide capacitance is much lower than a depletion capacitance in silicon. Therefore CG is independent on VBG. The value of q* decreases with increase in VBG after the channel inversion. Interestingly, the same behaviour is observed for the normalized values of ϕij, that is, ϕij/ϕ12. Figure 4c shows this comparison. These features can be explained by considering the trap's image charge20 and an electrical screening effect originating from the reduction of charges in the inversion layer of the channel, which allows ϕij and q* to be given by (see Methods).
where ϵ1 is the dielectric constant of SiO2, rij the distance between two trap sites and tacc the thickness of the inversion layer of the channel. Figure 4c shows the good agreement between the behaviour of ϕij and with tacc and rij equal to 0.4 and 2 nm respectively. This result means that all traps are located within a few nanometers of each other.
Derivation of power spectrum noise equations
More interestingly and importantly, the above-detailed analysis of q* and ϕij based on Coulomb repulsion provides us a better understanding of low-frequency noise in nanoscale MOSFETs19 and especially its deviation from the well-known 1/f noise. We address this noise issue, which can have useful implications for design and simulation of nanoscale MOSFETs. In large devices, with the assumption that 1/f noise is composed of an ensemble of a large number of RTSs originating from traps randomly distributed in space and potential level, the 1/f power spectrum current noise SI1 is given by17,19
where N is the number of active traps. This equation predicts an increase of noise with decreasing device area S, because CG and N (at a given trap density) scale with S. We measured the low-frequency noise at different VBG's (see Methods). A typical curve measured at VBG=16 V is shown in Figure 5a. The measured noise deviates from strict 1/f noise and is composed of a 1/f background noise superimposed by a Lorentzian shape related to the RTS noise generated by trap 3 for this peculiar bias VBG=16 V. An ultimate lower limit of equation (6) calculated for N=1 (one trap, albeit strictly speaking not valid for equation 6) with the gm, q* and CG values for the same VBG (trap 3) clearly overestimates the noise amplitude compared with the experimental data (Fig. 5a). When only a few traps are present in nanoscale devices, a better approach is to use the Machlup derivation2,6,21 of the Lorentzian equation from RTS. Thus, we can express the low-frequency power spectrum for trap i by (see Methods).
We calculated this quantity at 10 Hz for each trap, i=1 to 5, as a function of VBG using trap parameters (q*, CG) and the gi′ functions in Table 1 and Figure 3b. Each curve is in good agreement with the experimental data. Here τei is considered constant with the average value of τ listed in Table 1. The results are shown as bell-shaped curves and compared with the experimental data in Figure 5b. Each calculated curve is in good agreement with the experimental data. Note that traps 2 and 3 contribute to the noise spectra at 10 Hz for the same range of VBG but with a negligible contribution for trap 2. This is because trap 2 has a higher time constant than trap 3 (see Fig. 3a). As a consequence, the experimental data around VBG=10 V come from the 1/f background noise as also observed in Figure 5a. The discussion of the physical origin of this noise is out of the scope of this paper. We suggest elsewhere that it should be due to the dipolar polarization noise in the oxide. For the sake of device simulation, equation (7) is not very practical as it requires a detailed knowledge of the physical parameters of all defects involved in the device. A simplified expression of the maximum of equation (7) can be derived (see Methods) as
Equation (8) can be used to estimate the upper limit of noise as shown in Figure 5a,b. Especially, a gi′ value of 0.5 in equation (7) gives a good estimation of noise SImax at the corner frequency of the Lorentzian spectrum as shown in Figure 5a. This means that when just a few traps are active in nanoscale MOSFETs, the classical equations for 1/f noise (equation 6) should still be used in device simulation if compensated by a correction factor of about 0.08 as an upper approximation (equation 8).
Discussion
Among the ten measured samples, two did not have any RTS, six had a single RTS and two had many traps (RTSs) with one-by-one trap activation, one of which has been presented here. The second one is shown in Supplementary Figure S2 and an example of single trap is shown in Supplementary Figure S3. For a high-quality thermal oxide, the typical density of oxide traps is about 1010 cm−2 in an energy window of kT. These traps are mainly related to dangling bonds in SiO2 and at the Si/SiO2 interface22. Our device has a surface area of about 15×50 nm and an energy window CGΔVBG/CJavg=0.7 eV, where CJavg is the average of Table 1 and ΔVBG the window of back-gate voltages. Therefore, the statistical number of traps in our device can be estimated to 2.1, which is not so far from the experimental results from the statistical viewpoint.
One-by-one activation of RTSs demonstrated here and the corresponding noise reduction should also be relevant for any other NW-based devices, such as carbon nanotubes and other bottom-up compound semiconductor wires. However, the noise reported is still high23,24, compared with that state-of-the-art Si MOSFETs. This is because the nanotube in these devices is about 1 μm long, and thus there are many trap sites with no interaction (that is, Coulomb repulsion) between them. Therefore, for the lasting benefit of noise reduction, nanowire devices should have a few-ten-nanometer length, in which Coulomb repulsion between charges located at nearby trapping sites is effective.
Farmer et al.25 have reported the correlation between two RTS events. However, they did not give any detailed analysis for evaluating the RTS amplitude ΔI, the trap occupancy probabilities, the location of trap sites, the Coulomb term ϕij, the channel carrier screening effects or the influence on power spectrum noise. We were able to perform such an analysis, because the extremely small gate capacitor of the SOI-based MOSFETs enhances the Coulomb repulsion. Our detailed analysis allows a step-by-step evaluation of the above key parameters of each active trap in a nanoscale FET, and we propose a new model for the low-frequency noise of this nanoscale device suitable for device simulation. Therefore, this nanoscale MOSFET with a short channel and small gate capacitor can be used as a metrological tool for the analysis of capacitances and low-frequency noise. These approaches can be extended as well to devices composed of carbon nanotubes, graphene nanoribbons and any other state-of-the-art nanoscale structures.
Methods
Device fabrication
The nanoscale MOSFETs were fabricated on an SOI wafer. First, a narrow constriction sandwiched between two wider (400-nm wide) channels was patterned on the 30-nm-thick top silicon layer (p-type, boron concentration of 1015 cm−3). The length and width of the constriction channel were 30 and 60 nm, respectively (Fig. 1c). The patterning was followed by thermal oxidation at 1000 °C to form a 40-nm-thick SiO2 layer around the channel. This oxidation process reduced the size of the constriction to about 15 nm, giving a final channel dimension of 15×50 nm. Then, we implanted phosphorous ions outside the constriction, 5 μm away from it, using a resist mask to form highly doped source and drain regions. Finally, aluminium electrodes were evaporated on the source and drain regions.
Electrical measurements
Electrical measurements were performed at room temperature in a glove-box with a controlled N2 atmosphere (<1 p.p.m. of O2 and H2O). Drain voltage VD (usually 50 mV) and back gate voltage (<8 V) were applied with an ultralow-noise DC power supply (Shibasoku PA15A1 when VBG<8 V or Yokogawa 7651 when VBG>8 V). The source current was amplified with a DL 1211 current preamplifier supplied with batteries. RTS data and noise spectra were acquired with an Agilent 35670 dynamic signal analyzer (Agilent).
Determination of oxide trap depths
The trap depths are estimated by fitting with equation (3) the experimental trap occupancy. s obtained for each trap are listed in Table 1. In a parallel plate configuration, ≈ yti/tox, where yti is the trap depth and tox is the gate oxide thickness. The tox=400 nm is larger than width (W) and length (L) of the nanowire and we cannot neglect border effects. This induces a correction factor of 7.5. Therefore, yti≈CG.tox/(.7.5) as shown in Table 1.
Theoretical derivation of equation (5)
If VBG>VFB, an accumulation layer appears in the Si channel at the SiO2 interface. This affects the dielectric properties of the Si nanowire. An effective dielectric constant for Si is introduced to consider effects of screening by electrons in the channel. Considering the accumulation charge Qacc related to capacitance Cacc, surface potential ψs, the Debye screening length Ld and accumulation layer thickness tacc, we have
where W and L are the width and length of the nanowire, CG the back-gate capacitance (see Fig. 1c), k the Boltzmann constant, T the temperature, q the electron charge, VBG the back-gate voltage, VFB the flat-band voltage, ϵ0 the vacuum permittivity, ϵ2 the Si relative dielectric constant, and ϵ2′ the effective Si dielectric constant.
From equation (10), we get
The electric potential ϕij at a distance rij to the trap and rij′ to its image charge20 is
If we consider rij ≈ rij′ (in other words, the distance between traps is large compared to trap depth in oxide), we have
Combining equations (11) and (13), we have
Then the effective trapped charge q* is given by
In this work, the Debye screening length of the undoped silicon is very large (≫100 nm) compared with the Si thickness (15-nm-thick SOI), so we consider ϵ2≈ϵ1 and equation (14) is reduced to equation (5) in the text.
Theoretical derivation of equations (7) and (8)
We start from the Machlup derivation21 of power spectrum noise:
where ΔI is the RTS amplitude, τe and τc the trap emission and capture times, and f the frequency. Considering g=τe/(τc+τe) and ΔI/gm=q*/CG (see equations 1 and 2), we get
At the corner frequency of the Lorentzian distribution, 2πf(1−g)τe=1, and considering g=½, equation (18) becomes
Additional information
How to cite this article: Clément, N. et al. One-by-one trap activation in silicon nanowire transistors. Nat. Commun. 1:92 doi: 10.1038/ncomms1092 (2010).
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Acknowledgements
We thank C. Delerue of IEMN for theoretical discussions on Coulomb repulsion, and R. Leturcq, S. Pleutin, F. Alibart of IEMN and I. Mahboob of NTT for careful reading of the article.
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K.N. fabricated the devices; N.C. performed the electrical measurements; N.C. and K.N. analysed the data; N.C., K.N, A.F and D.V. discussed the results and wrote the article.
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Clément, N., Nishiguchi, K., Fujiwara, A. et al. One-by-one trap activation in silicon nanowire transistors. Nat Commun 1, 92 (2010). https://doi.org/10.1038/ncomms1092
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DOI: https://doi.org/10.1038/ncomms1092
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